It is well known that commercial processing procedures dictate maximum semiconductor chip size. It follows that the area of the chip is at a premium and, consequently, any improvement in area usage is significant. In integrated circuits, such as microprocessor chips in particular, where many functions are performed in a single chip, the proximity of the sites of cooperating functions to one another alone can be important because proper location may, for example, lead to shorter transmission paths and the sharing of those paths.
The present invention is directed at the problem of realizing necessary functions with relatively small chip areas in multifunction type integrated circuits of the microprocessor type. For example, a microprocessor includes a programable logic array (PLA) comprising a read-only memory (ROM) portion and a decoder portion which applies "address select" signals to the memory word lines in response to input signals applied by logic circuits external to the decoder portion. The memory and decoder portions of the PLA are alike in that they both are word organized and, typically, include ground lines interleaved with the word lines. Switch elements in the decoder portion formed at crosspoints between (word) lines which intersect the address lines cause grounding of ones of those intersecting word lines, through associated ground lines, when the associated switch elements are in the conductive state. For the decoder portion, input signals from an external logic circuit arrangement cause output signals to be applied to selected word lines of the memory portion depending on the pattern of grounded decoder word lines. Programable logic arrays are described in MOS/LSI Design and Application, Texas Instruments Electronics Series, by Carr and Mize, 1972, starting at page 229.
One problem with such arrangements is that a relatively large area is required to implement a PLA because a separate word line has been required hitherto for each set of signals to be applied to the memory portion by the decoder portion in response to each different input code. This one-to-one correspondence between word lines of the memory portion and input codes exists except in cases where input codes could be so assigned as to produce "don't-care" conditions. In the latter cases, a single word line may be responsive to more than one input code. But, in general, the assignment of input codes to take advantage of "don't-care" conditions is not always possible.